Integrated circuits includes more than millions devices in a specific area of a wafer and electrically connecting structure for connecting these devices to perform desired function. In order to achieve high performance integrated circuits or high package density of a wafer, the sizes of semiconductor devices have become smaller and smaller than before in the field of Ultra Large Scale Integrated (ULSI) technologies.
One of the typical devices is metal oxide semiconductor (MOS) field effect transistor. The MOS has been widely, traditionally applied in the semiconductor technologies. As well known in the art, the MOS includes a gate, a source and a drain. Similarly, in order to obtain high performance MOSFET, the MOS devices dimensions are continuously decreased to meet the requirement of the trend. Typically, the requirement of the devices towards high operation speed and low operation power. The devices are generally influenced by the RC delay and the source and drain resistance. For deep sub-micron meter MOS devices, the self-aligned silicide (SALICIDE) contacts are used for improving the operation speed.
Prior art proposed a high performance CMOS with CoSi.sub.2, NiSi as silicide for deep sub-micron high speed CMOS due to the low sheet resistance of fine silicide line. Self-aligned Ti silicided gate, source and drain process is one of the method for lowering the gate electrode sheet resistance and the source and drain resistance.
In conventional process for forming the SALICIDE on source and drain. A metal is typically formed on the surface of the substrate. For example, a metal layer, such as Ti, Pt, Co, W, Ni etc, is sputtered on the substrate, the gate structure. Then, a rapid thermal annealing (RTA) at 350 to 700 degrees centigrade is performed to react the metal with the gate and the substrate. Then, a stripping step is used to remove non-reactive refractory metal on the side wall spacers of the gate. Therefore, the SALICIDE layer, polycide layer are self-aligned formed on these regions. However, the SALICIDE on the source and drain will be formed into a portion of the substrate to a certain depth due to the silicon reacts with the metal. Generally speaking, this will cause junction leakage due to the depth of the source and drain junctions become too shallow. For deep sub-micron meter devices, this issue becomes more serious than ever.